The present application relates to time-to-digital converters and to circuit arrangements and apparatuses comprising time-to-digital converters as well as corresponding methods.
Time-to digital converters (TDCs) are electronic circuits which determine a time difference between predetermined features of two signals supplied to the time-to-digital converter. The features may for example comprise rising edges of the signals, falling edges of the signals, transitions from a logic zero to a logic one in the signals or transitions from a logic one to a logic zero in the signals.
Time-to-digital converters are for example employed in digital phase-locked loops (PLLs) as phase detectors for determining a phase difference between a reference signal and a signal fed back from an oscillator or in pulse modulation analog-to-digital converters.
In some cases, time-to-digital converters comprise a digital delay line, wherein after each delay element a sampling for example by digital comparators is performed. One of the two signals fed to the time-to-digital converter is fed to the delay line and propagates from delay element to delay element, which may be implemented as gates such that the signal then propagates from gate to gate. The other signal of the two signals fed to the time-to-digital converter triggers the comparators that sample the current state of the respective elements of the delay line. The number of delay elements B that are passed by the first signal before the second signal triggers the comparator is a measure for the time difference of the relevant features between the signals. This can be expressed byB=kTDC·ΔT, where B as mentioned above is the number of delay elements, i.e. the value, measured by the time-to-digital converter, and ΔT the time difference between the two relevant features of the signals. kTDC is the gain of the time-to-digital converter. For an absolute determination of ΔT, this gain has to be known. However, effects like noise on a power supply voltage supplying the time-to-digital converter and noise in the elements or components of the time-to-digital converter may temporarily change the signal propagation velocity in the delay line and, therefore, the gain of the time-to-digital converter. In particular, low frequency noise, for example 1/fnoise, may cause a slow drift of the time-to-digital converter gain. This may lead to a large long time error and, therefore, may adversely affect the functioning of a circuit arrangement like a PLL employing the time-to-digital converter.